Design of a Residue Number System Based Linear System Solver in Hardware

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F17%3A00304948" target="_blank" >RIV/68407700:21240/17:00304948 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1007/s11265-016-1146-1" target="_blank" >http://dx.doi.org/10.1007/s11265-016-1146-1</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1007/s11265-016-1146-1" target="_blank" >10.1007/s11265-016-1146-1</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Design of a Residue Number System Based Linear System Solver in Hardware

Popis výsledku v původním jazyce

This paper is focused on error-free solution of dense linear systems using residual arithmetic in hardware. The designed Modular System uses hardware identical Residual Processors (RP)s for solving independent systems of linear congruences and combines their solutions into the solution of the given linear system. This approach uses the residue number system which is based on the Chinese remainder theorem. In order to efficiently exploit parallel processing and cooperation of the individual components, a hardware architecture of the Modular System with several RPs is designed. In order to verify the proposed architecture, a Xilinx FPGA with a MicroBlaze processor was used. Experimental results are obtained for an evaluation FPGA board with Virtex 6. Results from implementation serve for subsequent theoretical analysis of the system performance for various linear system sizes and further improvement of the system. The proposed system can be useful as a special hardware peripheral or a part of an embedded system for solving large nonsingular systems of linear equations with integer, rational or floating-point coefficients with arbitrary precision.

Název v anglickém jazyce

Design of a Residue Number System Based Linear System Solver in Hardware

Popis výsledku anglicky

This paper is focused on error-free solution of dense linear systems using residual arithmetic in hardware. The designed Modular System uses hardware identical Residual Processors (RP)s for solving independent systems of linear congruences and combines their solutions into the solution of the given linear system. This approach uses the residue number system which is based on the Chinese remainder theorem. In order to efficiently exploit parallel processing and cooperation of the individual components, a hardware architecture of the Modular System with several RPs is designed. In order to verify the proposed architecture, a Xilinx FPGA with a MicroBlaze processor was used. Experimental results are obtained for an evaluation FPGA board with Virtex 6. Results from implementation serve for subsequent theoretical analysis of the system performance for various linear system sizes and further improvement of the system. The proposed system can be useful as a special hardware peripheral or a part of an embedded system for solving large nonsingular systems of linear equations with integer, rational or floating-point coefficients with arbitrary precision.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

<a href="/cs/project/GAP103%2F12%2F2377" target="_blank" >GAP103/12/2377: Studium vlastností residuální aritmetiky pro řešení soustav lineárních rovnic</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2017

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Journal of Signal Processing Systems

ISSN

1939-8018

e-ISSN

1939-8115

Svazek periodika

87

Číslo periodika v rámci svazku

3

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

14

Strana od-do

343-356

Kód UT WoS článku

000399451800006

EID výsledku v databázi Scopus

2-s2.0-84974818395