Error Masking Method Based On The Short-Duration Offline Test

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F17%3A00312125" target="_blank" >RIV/68407700:21240/17:00312125 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1016/j.micpro.2017.06.007" target="_blank" >http://dx.doi.org/10.1016/j.micpro.2017.06.007</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.micpro.2017.06.007" target="_blank" >10.1016/j.micpro.2017.06.007</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Error Masking Method Based On The Short-Duration Offline Test

Popis výsledku v původním jazyce

The method proposed in this article allows to construct error-masking fail-operational systems by com- bining time and area redundancy. In such a system, error detection is performed online, while error masking is achieved by a short-duration offline test. The time penalty caused by the offline test applies only when an error is detected. The error-masking ability in such a system is very close to TMR, the area overhead is smaller for a well defined class of circuits, and the delay penalty caused by the offline test remains reasonably small. The short-duration offline test is possible only when extensive design-for-test practices are used. Therefore, a novel gate structure is presented, which allows to construct combina- tional circuits testable by a short-duration offline test. The proposed test offers com plete fault coverage with respect to the stuck-on and stuck-open fault model. The proposed solutions are combined and a comprehensive description of the overall error-masking architecture is provided.

Název v anglickém jazyce

Error Masking Method Based On The Short-Duration Offline Test

Popis výsledku anglicky

The method proposed in this article allows to construct error-masking fail-operational systems by com- bining time and area redundancy. In such a system, error detection is performed online, while error masking is achieved by a short-duration offline test. The time penalty caused by the offline test applies only when an error is detected. The error-masking ability in such a system is very close to TMR, the area overhead is smaller for a well defined class of circuits, and the delay penalty caused by the offline test remains reasonably small. The short-duration offline test is possible only when extensive design-for-test practices are used. Therefore, a novel gate structure is presented, which allows to construct combina- tional circuits testable by a short-duration offline test. The proposed test offers com plete fault coverage with respect to the stuck-on and stuck-open fault model. The proposed solutions are combined and a comprehensive description of the overall error-masking architecture is provided.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/GA16-05179S" target="_blank" >GA16-05179S: Výzkum vztahů a společných vlastností spolehlivých a bezpečných architektur založených na programovatelných obvodech</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2017

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Microprocessors and Microsystems

ISSN

0141-9331

e-ISSN

1872-9436

Svazek periodika

52

Číslo periodika v rámci svazku

7

Stát vydavatele periodika

NL - Nizozemsko

Počet stran výsledku

15

Strana od-do

236-250

Kód UT WoS článku

000407984000020

EID výsledku v databázi Scopus

2-s2.0-85021293073