Parallel CRC optimisations on the x64 architecture: a per-partes method

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F24%3A00370040" target="_blank" >RIV/68407700:21240/24:00370040 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.1080/17445760.2023.2291349" target="_blank" >https://doi.org/10.1080/17445760.2023.2291349</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1080/17445760.2023.2291349" target="_blank" >10.1080/17445760.2023.2291349</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Parallel CRC optimisations on the x64 architecture: a per-partes method

Popis výsledku v původním jazyce

Each generation of CPU provides more resources and new features. These increase the ability to perform algorithms faster and with a higher degree of parallelism. The article discusses methods used to optimise CRC generation algorithms for long data blocks with consideration of the capabilities of contemporary systems. We analysed known software CRC algorithms and combined all known principles into a solution scalable in multiple CPU cores on single and multi-socket systems. Various algorithms were evaluated on contemporary multicore systems with 1 x 4, 1 x 64, 2 x 12, and 4 x 26 cores. The results show how the performance is affected by the architecture of the memory subsystem. Compared to the original sequential Sarwate algorithm, our algorithms are 48.0, 51.1, 38.0, and 28.8 times faster.

Název v anglickém jazyce

Parallel CRC optimisations on the x64 architecture: a per-partes method

Popis výsledku anglicky

Each generation of CPU provides more resources and new features. These increase the ability to perform algorithms faster and with a higher degree of parallelism. The article discusses methods used to optimise CRC generation algorithms for long data blocks with consideration of the capabilities of contemporary systems. We analysed known software CRC algorithms and combined all known principles into a solution scalable in multiple CPU cores on single and multi-socket systems. Various algorithms were evaluated on contemporary multicore systems with 1 x 4, 1 x 64, 2 x 12, and 4 x 26 cores. The results show how the performance is affected by the architecture of the memory subsystem. Compared to the original sequential Sarwate algorithm, our algorithms are 48.0, 51.1, 38.0, and 28.8 times faster.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2024

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

International Journal of Parallel, Emergent and Distributed Systems

ISSN

1744-5760

e-ISSN

—

Svazek periodika

39

Číslo periodika v rámci svazku

3

Stát vydavatele periodika

GB - Spojené království Velké Británie a Severního Irska

Počet stran výsledku

25

Strana od-do

292-316

Kód UT WoS článku

001124654100001

EID výsledku v databázi Scopus

2-s2.0-85179744962