RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21340%2F25%3A00383921" target="_blank" >RIV/68407700:21340/25:00383921 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.1088/1748-0221/20/03/P03024" target="_blank" >https://doi.org/10.1088/1748-0221/20/03/P03024</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1088/1748-0221/20/03/P03024" target="_blank" >10.1088/1748-0221/20/03/P03024</a>

Jazyk výsledku

angličtina

Název v původním jazyce

RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades

Popis výsledku v původním jazyce

The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 x 50 μm2 pixels for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN. A common architecture, design and verification framework has been developed to enable final pixel chips of different sizes to be designed, verified and tested to handle extreme hit rates of 3 GHz/cm2 (up to 12 GHz per chip) together with an increased trigger rate of 1 MHz and efficient readout of up to 5.12 Gbits/s per pixel chip. Tolerance to an extremely hostile radiation environment with 1 Grad over 10 years and induced SEU (Single Event Upset) rates of up to 100 upsets per second per chip have been major challenges to make reliable pixel chips. Three generations of pixel chips, and many specific mixed signal building blocks and radiation test chips, have been submitted and extensively tested to get to final production chips. The large, complex and high rate pixel chips have been developed with a strong emphasis on low power consumption together with a concurrent development and qualification of novel serial powering at chip, module and system level, to minimize detector material budget.

Název v anglickém jazyce

RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades

Popis výsledku anglicky

The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 x 50 μm2 pixels for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN. A common architecture, design and verification framework has been developed to enable final pixel chips of different sizes to be designed, verified and tested to handle extreme hit rates of 3 GHz/cm2 (up to 12 GHz per chip) together with an increased trigger rate of 1 MHz and efficient readout of up to 5.12 Gbits/s per pixel chip. Tolerance to an extremely hostile radiation environment with 1 Grad over 10 years and induced SEU (Single Event Upset) rates of up to 100 upsets per second per chip have been major challenges to make reliable pixel chips. Three generations of pixel chips, and many specific mixed signal building blocks and radiation test chips, have been submitted and extensively tested to get to final production chips. The large, complex and high rate pixel chips have been developed with a strong emphasis on low power consumption together with a concurrent development and qualification of novel serial powering at chip, module and system level, to minimize detector material budget.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

—

Návaznosti

—

Rok uplatnění

2025

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Journal of Instrumentation

ISSN

1748-0221

e-ISSN

1748-0221

Svazek periodika

20

Číslo periodika v rámci svazku

3

Stát vydavatele periodika

GB - Spojené království Velké Británie a Severního Irska

Počet stran výsledku

67

Strana od-do

1-67

Kód UT WoS článku

001458719200001

EID výsledku v databázi Scopus

2-s2.0-105000463290