The FPGA Implementation of Dictionary; HW Consumption Versus Latency

Kód výsledku v IS VaVaI

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Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

The FPGA Implementation of Dictionary; HW Consumption Versus Latency

Popis výsledku v původním jazyce

This paper presents a study on the possibilities of dictionary implementation for a dictionary compression system in FPGA. The possibilities of creation of the dictionary using the registers and the RAM memory are described. For these implementations, the interdependence of hardware consumption and latency during basic dictionary processes like writing, reading and searching a match is described. With regard to the hardware consumption, RAM dictionary implementation is the most effective. On the contrary, dictionary implementation by the registers is more suitable with regard to the latency during searching the matches in the dictionary. For these reasons, the combination of both implementation approaches was implemented. The core of the dictionary isin RAM memory and the searching part is implemented by the registers. This part is similar to a hash table. It is implemented by the parallel shift registers to minimize the searching latency.

Název v anglickém jazyce

The FPGA Implementation of Dictionary; HW Consumption Versus Latency

Popis výsledku anglicky

This paper presents a study on the possibilities of dictionary implementation for a dictionary compression system in FPGA. The possibilities of creation of the dictionary using the registers and the RAM memory are described. For these implementations, the interdependence of hardware consumption and latency during basic dictionary processes like writing, reading and searching a match is described. With regard to the hardware consumption, RAM dictionary implementation is the most effective. On the contrary, dictionary implementation by the registers is more suitable with regard to the latency during searching the matches in the dictionary. For these reasons, the combination of both implementation approaches was implemented. The core of the dictionary isin RAM memory and the searching part is implemented by the registers. This part is similar to a hash table. It is implemented by the parallel shift registers to minimize the searching latency.

Druh

D - Stať ve sborníku

CEP obor

JA - Elektronika a optoelektronika, elektrotechnika

OECD FORD obor

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Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2013

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of The 36th International Conference on Telecommunications and Signal Processing

ISBN

978-1-4799-0403-7

ISSN

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e-ISSN

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Počet stran výsledku

4

Strana od-do

82-86

Název nakladatele

Neuveden

Místo vydání

Neuveden

Místo konání akce

Rome

Datum konání akce

2. 7. 2013

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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