Design of a High-Throughput Match Search Unit for Lossless Compression Algorithms
Identifikátory výsledku
Kód výsledku v IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F19%3A10133189" target="_blank" >RIV/63839172:_____/19:10133189 - isvavai.cz</a>
Nalezeny alternativní kódy
RIV/68407700:21240/19:00326313
Výsledek na webu
<a href="http://dx.doi.org/10.1109/CCWC.2019.8666521" target="_blank" >http://dx.doi.org/10.1109/CCWC.2019.8666521</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/CCWC.2019.8666521" target="_blank" >10.1109/CCWC.2019.8666521</a>
Alternativní jazyky
Jazyk výsledku
angličtina
Název v původním jazyce
Design of a High-Throughput Match Search Unit for Lossless Compression Algorithms
Popis výsledku v původním jazyce
This paper presents an attempt to combine recent research in fields of hardware-and software-based high-throughput universal lossless compression algorithms and their implementations, resulting into a case study focusing on one of the most critical parts of compression algorithms - a Match Search Unit (MSU) and its parallelization. The presented FPGA design combines ideas of the LZ4 algorithm (which is derived from the most common LZ77) with the state of the art hardware architectures for lossless compression also based on LZ77. This approach might lead to a smaller, better organized or more efficient "building block" for modern implementations of hardware driven lossless compression algorithms. The presented design focuses on optimization of the main problem of the LZ77 family, namely the construction of and searching in a compression dictionary. Particularly, we combine a Live Value Table (LVT) with multi-ported memory in order to improve the bandwidth of the dictionary and the Fibonacci hashing principle originating from LZ4 algorithm to decrease latency of the MSU and to achieve overall higher throughput rate. For the design synthesis an FPGA of the Xilinx Virtex-7 family was used.
Název v anglickém jazyce
Design of a High-Throughput Match Search Unit for Lossless Compression Algorithms
Popis výsledku anglicky
This paper presents an attempt to combine recent research in fields of hardware-and software-based high-throughput universal lossless compression algorithms and their implementations, resulting into a case study focusing on one of the most critical parts of compression algorithms - a Match Search Unit (MSU) and its parallelization. The presented FPGA design combines ideas of the LZ4 algorithm (which is derived from the most common LZ77) with the state of the art hardware architectures for lossless compression also based on LZ77. This approach might lead to a smaller, better organized or more efficient "building block" for modern implementations of hardware driven lossless compression algorithms. The presented design focuses on optimization of the main problem of the LZ77 family, namely the construction of and searching in a compression dictionary. Particularly, we combine a Live Value Table (LVT) with multi-ported memory in order to improve the bandwidth of the dictionary and the Fibonacci hashing principle originating from LZ4 algorithm to decrease latency of the MSU and to achieve overall higher throughput rate. For the design synthesis an FPGA of the Xilinx Virtex-7 family was used.
Klasifikace
Druh
D - Stať ve sborníku
CEP obor
—
OECD FORD obor
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Návaznosti výsledku
Projekt
<a href="/cs/project/EF16_013%2F0001797" target="_blank" >EF16_013/0001797: E-infrastruktura CESNET - modernizace</a><br>
Návaznosti
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Ostatní
Rok uplatnění
2019
Kód důvěrnosti údajů
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Údaje specifické pro druh výsledku
Název statě ve sborníku
2019 IEEE 9TH ANNUAL COMPUTING AND COMMUNICATION WORKSHOP AND CONFERENCE (CCWC)
ISBN
978-1-72810-554-3
ISSN
—
e-ISSN
—
Počet stran výsledku
7
Strana od-do
732-738
Název nakladatele
IEEE
Místo vydání
Las Vegas, NV, USA
Místo konání akce
Las Vegas, NV, USA
Datum konání akce
7. 1. 2019
Typ akce podle státní příslušnosti
WRD - Celosvětová akce
Kód UT WoS článku
000469462800120