The analysis of reliability of solder joints on SMD ceramic resistor arrays

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F17%3APU124340" target="_blank" >RIV/00216305:26220/17:PU124340 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.scopus.com/record/display.uri?eid=2-s2.0-85029894081&origin=resultslist&sort=plf-f&src=s&st1=Three+ways+to+ceramic+packages&st2=&sid=534787b9a245c56e0a007da102eef45d&sot=b&sdt=b&sl=45&s=TITLE-ABS-KEY%28Three+ways+to+ceramic+packages%29&relpos" target="_blank" >https://www.scopus.com/record/display.uri?eid=2-s2.0-85029894081&origin=resultslist&sort=plf-f&src=s&st1=Three+ways+to+ceramic+packages&st2=&sid=534787b9a245c56e0a007da102eef45d&sot=b&sdt=b&sl=45&s=TITLE-ABS-KEY%28Three+ways+to+ceramic+packages%29&relpos</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ISSE.2017.8000939" target="_blank" >10.1109/ISSE.2017.8000939</a>

Jazyk výsledku

angličtina

Název v původním jazyce

The analysis of reliability of solder joints on SMD ceramic resistor arrays

Popis výsledku v původním jazyce

Abstract This paper deals with the area of solder joints reliability and narrower focus is on solder joints on SMD ceramic resistor arrays in configuration 8x0603. These SMD ceramic resistor arrays are soldered on 30 testing boards and every board includes two packages. Testing boards are exposed to influences of temperature changes in the temperature chamber. The range of temperature changes is from -25 °C to 120 °C with 15 minutes time dwell on minimal and maximal temperature. Each SMD ceramic package includes eight independent resistors with zero resistance and there is monitored the conductive connection between each pair of solder joints on each resistor. The main aim is to trace reliability of solder joints depending on the location of solder joints on SMD ceramic package. There is an assumption that the highest reliability of solder joints is in the centre of the package and decreases towards corners of the package. The next section shows computer simulations of testing boards, SMD ceramic packages and solder joints on them. The prerequisite for simulations is to achieve similar conditions such as during temperature cycling in the chamber. This includes same temperature conditions as in the case of the practical experiment and using the model which is close to real SMD ceramic resistor array. The results from the practical experiment are complemented by simulations in ANSYS.

Název v anglickém jazyce

The analysis of reliability of solder joints on SMD ceramic resistor arrays

Popis výsledku anglicky

Abstract This paper deals with the area of solder joints reliability and narrower focus is on solder joints on SMD ceramic resistor arrays in configuration 8x0603. These SMD ceramic resistor arrays are soldered on 30 testing boards and every board includes two packages. Testing boards are exposed to influences of temperature changes in the temperature chamber. The range of temperature changes is from -25 °C to 120 °C with 15 minutes time dwell on minimal and maximal temperature. Each SMD ceramic package includes eight independent resistors with zero resistance and there is monitored the conductive connection between each pair of solder joints on each resistor. The main aim is to trace reliability of solder joints depending on the location of solder joints on SMD ceramic package. There is an assumption that the highest reliability of solder joints is in the centre of the package and decreases towards corners of the package. The next section shows computer simulations of testing boards, SMD ceramic packages and solder joints on them. The prerequisite for simulations is to achieve similar conditions such as during temperature cycling in the chamber. This includes same temperature conditions as in the case of the practical experiment and using the model which is close to real SMD ceramic resistor array. The results from the practical experiment are complemented by simulations in ANSYS.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2017

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Electronics Technology (ISSE), 2017 40th International Spring Seminar

ISBN

978-1-5386-0582-0

ISSN

2161-2528

e-ISSN

—

Počet stran výsledku

5

Strana od-do

240-245

Název nakladatele

IEEE Computer Society

Místo vydání

Sofia, Bulgaria

Místo konání akce

Sofia

Datum konání akce

10. 5. 2017

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000426973000062