Saving area and power consumption in 65 nm digital standard cell library

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F22%3APU150969" target="_blank" >RIV/00216305:26220/22:PU150969 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.eeict.cz/eeict_download/archiv/sborniky/EEICT_2022_sbornik_1_v2.pdf" target="_blank" >https://www.eeict.cz/eeict_download/archiv/sborniky/EEICT_2022_sbornik_1_v2.pdf</a>

DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Saving area and power consumption in 65 nm digital standard cell library

Popis výsledku v původním jazyce

This study aims to investigate multi-bit pulsed latches in comparison with multi-bit flip flops as one of the low-power solutions in 65 nm technology process. Topologies of pulse generators and multi-bit pulsed latches were investigated to find out which can be more suitable. The pulse generator was chosen because of its low power and a small area in comparison with other options. The pulse generator is made of a simple AND logical gate and a double-stacked inverter. The pulsed latch was also chosen because of its low power, small area, and reliability of the circuit. The chosen topology is modified PPCLA. Simulations of the chosen topology had shown that multi-bit flip flops could be replaced with more effective multi-bit pulsed latches.

Název v anglickém jazyce

Saving area and power consumption in 65 nm digital standard cell library

Popis výsledku anglicky

This study aims to investigate multi-bit pulsed latches in comparison with multi-bit flip flops as one of the low-power solutions in 65 nm technology process. Topologies of pulse generators and multi-bit pulsed latches were investigated to find out which can be more suitable. The pulse generator was chosen because of its low power and a small area in comparison with other options. The pulse generator is made of a simple AND logical gate and a double-stacked inverter. The pulsed latch was also chosen because of its low power, small area, and reliability of the circuit. The chosen topology is modified PPCLA. Simulations of the chosen topology had shown that multi-bit flip flops could be replaced with more effective multi-bit pulsed latches.

Druh

D - Stať ve sborníku

CEP obor

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OECD FORD obor

20200 - Electrical engineering, Electronic engineering, Information engineering

Projekt

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Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2022

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings I of the 28th Conference STUDENT EEICT 2022 General papers

ISBN

978-80-214-6029-4

ISSN

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e-ISSN

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Počet stran výsledku

4

Strana od-do

190-193

Název nakladatele

Brno University of Technology, Faculty of Electrical Engineering and Communicatiopn

Místo vydání

Brno

Místo konání akce

Brno

Datum konání akce

26. 4. 2022

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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