Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery
Identifikátory výsledku
Kód výsledku v IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F19%3APU132059" target="_blank" >RIV/00216305:26230/19:PU132059 - isvavai.cz</a>
Výsledek na webu
<a href="https://www.fit.vut.cz/research/publication/11879/" target="_blank" >https://www.fit.vut.cz/research/publication/11879/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/LATW.2019.8704639" target="_blank" >10.1109/LATW.2019.8704639</a>
Alternativní jazyky
Jazyk výsledku
angličtina
Název v původním jazyce
Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery
Popis výsledku v původním jazyce
Triple Modular Redundancy (TMR) applied with various granularity combined with periodical scrubbing of a configuration memory or with run-time Partial Dynamic Reconfiguration (PDR) for fault recovery are one of the most preferred Single Event Upset (SEU) mitigation techniques used by Fault Tolerant Systems (FTS) implemented into SRAM-based FPGAs. Usage of PDR and TMR allows recovering of FTSs from all transient SEU faults and offers run-time fault mitigation compared to scrubbing methods which only correct configuration upsets and are limited by scrubbing period latency. Reconfigurable TMR architecture may require global state maintenance after PDR is applied for fault removal. In such situation, operational state of reconfigured circuit copy needs to be synchronized with remaining circuit copies which were active during PDR. This paper evaluates existing synchronization methods for reconfigurable TMR architectures and soft-core processors; presents our recent research focused on a state synchronization methodology compared to the state of the art methods and further investigates strategy for a state synchronization of TMR-protected soft-core processor neo430.
Název v anglickém jazyce
Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery
Popis výsledku anglicky
Triple Modular Redundancy (TMR) applied with various granularity combined with periodical scrubbing of a configuration memory or with run-time Partial Dynamic Reconfiguration (PDR) for fault recovery are one of the most preferred Single Event Upset (SEU) mitigation techniques used by Fault Tolerant Systems (FTS) implemented into SRAM-based FPGAs. Usage of PDR and TMR allows recovering of FTSs from all transient SEU faults and offers run-time fault mitigation compared to scrubbing methods which only correct configuration upsets and are limited by scrubbing period latency. Reconfigurable TMR architecture may require global state maintenance after PDR is applied for fault removal. In such situation, operational state of reconfigured circuit copy needs to be synchronized with remaining circuit copies which were active during PDR. This paper evaluates existing synchronization methods for reconfigurable TMR architectures and soft-core processors; presents our recent research focused on a state synchronization methodology compared to the state of the art methods and further investigates strategy for a state synchronization of TMR-protected soft-core processor neo430.
Klasifikace
Druh
D - Stať ve sborníku
CEP obor
—
OECD FORD obor
20206 - Computer hardware and architecture
Návaznosti výsledku
Projekt
<a href="/cs/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>
Návaznosti
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Ostatní
Rok uplatnění
2019
Kód důvěrnosti údajů
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Údaje specifické pro druh výsledku
Název statě ve sborníku
20th IEEE Latin American Test Symposium (LATS 2019)
ISBN
978-1-7281-1756-0
ISSN
—
e-ISSN
—
Počet stran výsledku
4
Strana od-do
32-35
Název nakladatele
IEEE Computer Society
Místo vydání
Santiago
Místo konání akce
Hotel Fundador, Santiago de Chile
Datum konání akce
11. 3. 2019
Typ akce podle státní příslušnosti
WRD - Celosvětová akce
Kód UT WoS článku
000469850000036