Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor neo430

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F19%3APU132060" target="_blank" >RIV/00216305:26230/19:PU132060 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.fit.vut.cz/research/publication/11905/" target="_blank" >https://www.fit.vut.cz/research/publication/11905/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DDECS.2019.8724636" target="_blank" >10.1109/DDECS.2019.8724636</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor neo430

Popis výsledku v původním jazyce

Reconfigurable fault tolerant (FT) architecture can be implemented into SRAM FPGA by using combination of Partial Dynamic Reconfiguration (PDR) and Triple Modular Redundancy (TMR). SRAM FPGAs are susceptible to Single Event Upsets (SEUs) which are the most common transient faults induced by cosmic radiation. SEU mitigation mechanism is required when SRAM FPGAs are integrated into safety-critical systems. An essential requirement for these systems is often to remain fail-operational and perform implemented functionality after the occurrence of a fault. In our research, we proposed a run-time FT architecture based on coarse-grained TMR with triplicated soft-core processor neo430, PDR for removing all transient SEU faults and the state synchronization allowing smooth state recovery from the inconsistent state when reconfiguration of failed processor instance was finished into the state where all three processors operate synchronously. This paper describes developed FT architecture and fault recovery strategy performing all necessary steps run-time and without additional blocking of the system functionality. The state synchronization for soft-core processor neo430 architecture is described in detail. Moreover, the paper presents developed PDR framework used for validation of proposed fault recovery strategy.

Název v anglickém jazyce

Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor neo430

Popis výsledku anglicky

Reconfigurable fault tolerant (FT) architecture can be implemented into SRAM FPGA by using combination of Partial Dynamic Reconfiguration (PDR) and Triple Modular Redundancy (TMR). SRAM FPGAs are susceptible to Single Event Upsets (SEUs) which are the most common transient faults induced by cosmic radiation. SEU mitigation mechanism is required when SRAM FPGAs are integrated into safety-critical systems. An essential requirement for these systems is often to remain fail-operational and perform implemented functionality after the occurrence of a fault. In our research, we proposed a run-time FT architecture based on coarse-grained TMR with triplicated soft-core processor neo430, PDR for removing all transient SEU faults and the state synchronization allowing smooth state recovery from the inconsistent state when reconfiguration of failed processor instance was finished into the state where all three processors operate synchronously. This paper describes developed FT architecture and fault recovery strategy performing all necessary steps run-time and without additional blocking of the system functionality. The state synchronization for soft-core processor neo430 architecture is described in detail. Moreover, the paper presents developed PDR framework used for validation of proposed fault recovery strategy.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2019

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019)

ISBN

978-1-7281-0073-9

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

136-140

Název nakladatele

IEEE Computer Society

Místo vydání

Cluj-Napoca

Místo konání akce

Cluj-Napoca

Datum konání akce

24. 4. 2019

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000492839800003