The Fault-tolerant Single-FPGA Systems with a Self-repair Reconfiguration Controller

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F23%3APU149351" target="_blank" >RIV/00216305:26230/23:PU149351 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.fit.vut.cz/research/publication/12822/" target="_blank" >https://www.fit.vut.cz/research/publication/12822/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/LASCAS56464.2023.10108372" target="_blank" >10.1109/LASCAS56464.2023.10108372</a>

Jazyk výsledku

angličtina

Název v původním jazyce

The Fault-tolerant Single-FPGA Systems with a Self-repair Reconfiguration Controller

Popis výsledku v původním jazyce

Fault tolerance in electronic systems is essential in harsh environments such as space. However, FPGAs that can be used to accelerate various computations are prone to configuration memory failures that determine their function. Repairing these failures is essential to increase system resilience. For this purpose, the partial dynamic reconfiguration controller is necessary. To design a comprehensive system inside one FPGA, we force the controller to be on the same FPGA with a payload circuit. We create and thoroughly test a new reconfiguration controller to increase the system's resiliency with the ability to repair itself during its own operation. For this purpose, the FPGA controller is in coarse-grained triple modular redundancy to be able to recover despite the failure of any of its modules. The proposed controller has been tested to increase the resilience of circuits from a set of benchmark circuits. The entire system with the controller was evaluated on an actual FPGA, where faults were injected directly into the configuration memory of this FPGA. Reliability parameters are measured by a platform designed for this purpose, partly directly on the tested FPGA. As we can see from the results, the mean time to failure has been increased by up to 69% compared to a system equipped with only triple modular redundancy with a reasonable amount of hardware resources. The competitive solution brings only a 42% improvement in resilience with the same parameters.

Název v anglickém jazyce

The Fault-tolerant Single-FPGA Systems with a Self-repair Reconfiguration Controller

Popis výsledku anglicky

Fault tolerance in electronic systems is essential in harsh environments such as space. However, FPGAs that can be used to accelerate various computations are prone to configuration memory failures that determine their function. Repairing these failures is essential to increase system resilience. For this purpose, the partial dynamic reconfiguration controller is necessary. To design a comprehensive system inside one FPGA, we force the controller to be on the same FPGA with a payload circuit. We create and thoroughly test a new reconfiguration controller to increase the system's resiliency with the ability to repair itself during its own operation. For this purpose, the FPGA controller is in coarse-grained triple modular redundancy to be able to recover despite the failure of any of its modules. The proposed controller has been tested to increase the resilience of circuits from a set of benchmark circuits. The entire system with the controller was evaluated on an actual FPGA, where faults were injected directly into the configuration memory of this FPGA. Reliability parameters are measured by a platform designed for this purpose, partly directly on the tested FPGA. As we can see from the results, the mean time to failure has been increased by up to 69% compared to a system equipped with only triple modular redundancy with a reasonable amount of hardware resources. The competitive solution brings only a 42% improvement in resilience with the same parameters.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2023

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

LASCAS 2023 - 14th IEEE Latin American Symposium on Circuits and Systems, Proceedings

ISBN

978-1-6654-5705-7

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

104-107

Název nakladatele

Institute of Electrical and Electronics Engineers

Místo vydání

Quito

Místo konání akce

QUITO, ECUADOR

Datum konání akce

28. 2. 2023

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000990483600026