Test response compaction method with improved detection and diagnostic abilities

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F46747885%3A24220%2F18%3A00004392" target="_blank" >RIV/46747885:24220/18:00004392 - isvavai.cz</a>

Výsledek na webu

<a href="https://api.elsevier.com/content/article/eid/1-s2.0-S0026271417304924" target="_blank" >https://api.elsevier.com/content/article/eid/1-s2.0-S0026271417304924</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.microrel.2017.10.016" target="_blank" >10.1016/j.microrel.2017.10.016</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Test response compaction method with improved detection and diagnostic abilities

Popis výsledku v původním jazyce

This paper describes a test response compaction method that preserves diagnostic information and enables performing a test-per-clock offline test. The test response compaction system is based on a chain of T flip-flops. The T flip-flop signature chain can preserve the information about the positions of the erroneous test response occurrence and the information about the clock cycle when the erroneous test responses occurred. This information can be used for diagnostic purposes. An algorithm that localizes errors according to the T flip-flop chain output is presented. The paper discusses the possible benefits and limitations of the proposed test pattern compaction scheme. The influence of multiple errors on detection and localization capability of the compaction system and hardware overhead is discussed in the paper as well. The probability of error masking is analyzed, the proposed scheme provides substantially lower masking probability than a D flip-flop chain and a MISR. The scheme can spare the test time by the test-per-clock arrangement. The hardware overhead and reached test time are given for several benchmark circuits in the paper as well.

Název v anglickém jazyce

Test response compaction method with improved detection and diagnostic abilities

Popis výsledku anglicky

This paper describes a test response compaction method that preserves diagnostic information and enables performing a test-per-clock offline test. The test response compaction system is based on a chain of T flip-flops. The T flip-flop signature chain can preserve the information about the positions of the erroneous test response occurrence and the information about the clock cycle when the erroneous test responses occurred. This information can be used for diagnostic purposes. An algorithm that localizes errors according to the T flip-flop chain output is presented. The paper discusses the possible benefits and limitations of the proposed test pattern compaction scheme. The influence of multiple errors on detection and localization capability of the compaction system and hardware overhead is discussed in the paper as well. The probability of error masking is analyzed, the proposed scheme provides substantially lower masking probability than a D flip-flop chain and a MISR. The scheme can spare the test time by the test-per-clock arrangement. The hardware overhead and reached test time are given for several benchmark circuits in the paper as well.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Microelectronics Reliability

ISSN

0026-2714

e-ISSN

—

Svazek periodika

80

Číslo periodika v rámci svazku

JA

Stát vydavatele periodika

NL - Nizozemsko

Počet stran výsledku

8

Strana od-do

249-256

Kód UT WoS článku

000423891400030

EID výsledku v databázi Scopus

2-s2.0-85034271519