Pseudo-Random Pattern Generator Design for Column Matching BIST

Kód výsledku v IS VaVaI

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Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Pseudo-Random Pattern Generator Design for Column Matching BIST

Popis výsledku v původním jazyce

This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built in self-test design method. The pattern generator should be as small as possible, whereas patternsgenerated by it should guarantee satisfactory fault coverage. Weighted random pattern generators offer this. Several weighted pattern generator designs are proposed and their effectiveness is evaluated in this paper. Moreover, two methods for computing the weights are compared. The column-matching method is primarily intended for a test-per-clock BIST, i.e., test patterns are applied to the tested circuit in parallel. Pseudorandom vectors obtained by an LFSR are modified here by a combinational circuit,to obtain deterministic test patterns. The number of inputs of this block corresponds to the width of the LFSR, the outputs correspond to the tested circuit inputs. This paper discusses possibilities of a reduction of the LFSR width.

Název v anglickém jazyce

Pseudo-Random Pattern Generator Design for Column Matching BIST

Popis výsledku anglicky

This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built in self-test design method. The pattern generator should be as small as possible, whereas patternsgenerated by it should guarantee satisfactory fault coverage. Weighted random pattern generators offer this. Several weighted pattern generator designs are proposed and their effectiveness is evaluated in this paper. Moreover, two methods for computing the weights are compared. The column-matching method is primarily intended for a test-per-clock BIST, i.e., test patterns are applied to the tested circuit in parallel. Pseudorandom vectors obtained by an LFSR are modified here by a combinational circuit,to obtain deterministic test patterns. The number of inputs of this block corresponds to the width of the LFSR, the outputs correspond to the tested circuit inputs. This paper discusses possibilities of a reduction of the LFSR width.

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

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Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2007

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of 10th Euromicro Conference on Digital System Design

ISBN

0-7695-2978-X

ISSN

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e-ISSN

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Počet stran výsledku

7

Strana od-do

657-663

Název nakladatele

IEEE Computer Society

Místo vydání

Los Alamitos

Místo konání akce

Lübeck

Datum konání akce

27. 8. 2007

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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