MOSFET gate dimension dependent drain and source leakage modeling by standard SPICE models

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F13%3A00204873" target="_blank" >RIV/68407700:21230/13:00204873 - isvavai.cz</a>

Výsledek na webu

<a href="http://www.sciencedirect.com/science/journal/00381101/81" target="_blank" >http://www.sciencedirect.com/science/journal/00381101/81</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.sse.2013.01.001" target="_blank" >10.1016/j.sse.2013.01.001</a>

Jazyk výsledku

angličtina

Název v původním jazyce

MOSFET gate dimension dependent drain and source leakage modeling by standard SPICE models

Popis výsledku v původním jazyce

The leakage current in standard MOSFET models (BSIM3/BSIM4) is typically modeled by drain?bulk and source?bulk diodes. This modeling method does not consider the impact of several parasitic bipolar devices. For the accurate modeling the impact of the following bipolar transistors has to be considered: a lateral bipolar transistor drain?bulk?source, a vertical bipolar transistor drain?bulk-substrate (only in isolated structures), and a vertical bipolar transistor source?bulk-substrate (only in isolated structures). For example, the drain or source leakage as a function of gate length cannot be modeled without the scalable parasitic bipolar devices. This contribution demonstrates the structure of a proposed macro model, implemented scalability (in most cases nonlinear), developed scaling equations, and physical explanation of this scaling. Finally, the comparison of measured data vs. simulation is presented in order to confirm the model validity. This model improvement solves not only le

Název v anglickém jazyce

MOSFET gate dimension dependent drain and source leakage modeling by standard SPICE models

Popis výsledku anglicky

The leakage current in standard MOSFET models (BSIM3/BSIM4) is typically modeled by drain?bulk and source?bulk diodes. This modeling method does not consider the impact of several parasitic bipolar devices. For the accurate modeling the impact of the following bipolar transistors has to be considered: a lateral bipolar transistor drain?bulk?source, a vertical bipolar transistor drain?bulk-substrate (only in isolated structures), and a vertical bipolar transistor source?bulk-substrate (only in isolated structures). For example, the drain or source leakage as a function of gate length cannot be modeled without the scalable parasitic bipolar devices. This contribution demonstrates the structure of a proposed macro model, implemented scalability (in most cases nonlinear), developed scaling equations, and physical explanation of this scaling. Finally, the comparison of measured data vs. simulation is presented in order to confirm the model validity. This model improvement solves not only le

Druh

J_x - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)

CEP obor

JA - Elektronika a optoelektronika, elektrotechnika

OECD FORD obor

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Projekt

<a href="/cs/project/GAP102%2F10%2F1665" target="_blank" >GAP102/10/1665: Symbolické a semisymbolické metody pro výkonové a mechatronické aplikace</a><br>

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2013

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Solid-State Electronics

ISSN

0038-1101

e-ISSN

—

Svazek periodika

81

Číslo periodika v rámci svazku

3

Stát vydavatele periodika

NL - Nizozemsko

Počet stran výsledku

7

Strana od-do

144-150

Kód UT WoS článku

000317444400026

EID výsledku v databázi Scopus

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