Dislocation-Induced Punchthrough Causing Drain-to-Source Leakage Current in Power VD MOSFET Structures

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21340%2F16%3A00311342" target="_blank" >RIV/68407700:21340/16:00311342 - isvavai.cz</a>

Výsledek na webu

<a href="http://ieeexplore.ieee.org/document/7523322/?reload=true" target="_blank" >http://ieeexplore.ieee.org/document/7523322/?reload=true</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/TDMR.2016.2594484" target="_blank" >10.1109/TDMR.2016.2594484</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Dislocation-Induced Punchthrough Causing Drain-to-Source Leakage Current in Power VD MOSFET Structures

Popis výsledku v původním jazyce

A detailed characterization of the leakage in semiconductor devices is essential for proper adjustment of the manufacturing process in order to eliminate the leakage. Subsurface punchthrough was determined as the leakage current mechanism in the power vertical double-diffused metal-oxide-semiconductor field-effect-transistor, and the quadratic dependence of the drain current was confirmed for the leakage caused by the punchthrough. A failure analysis revealed a large number of dislocations located in the corners of transistor cells. The majority of the detected dislocations were electrically inactive. Dislocation depth measurement indicated that only a small number of the dislocations penetrated deep into the channel, i.e., penetrated from source area to the boron-doped p-transistor channel. The transistor channel shortening caused by the enhanced phosphorus diffusion along the dislocations was determined as the root cause of the leakage. The diffusion spikes of the phosphorus atoms lengthened the n+ source layer, and the interface of the n+ and p-layer was shifted into the transistor channel at the site of the dislocation. Manufacturing process experiments related to the channel lengthening and the channel doping confirmed the theory of the dislocation-induced channel shortening. The occurrence of dislocations was attributed to the surface stress induced by the improper conditions of oxide growing and plasma etching in the affected regions.

Název v anglickém jazyce

Dislocation-Induced Punchthrough Causing Drain-to-Source Leakage Current in Power VD MOSFET Structures

Popis výsledku anglicky

A detailed characterization of the leakage in semiconductor devices is essential for proper adjustment of the manufacturing process in order to eliminate the leakage. Subsurface punchthrough was determined as the leakage current mechanism in the power vertical double-diffused metal-oxide-semiconductor field-effect-transistor, and the quadratic dependence of the drain current was confirmed for the leakage caused by the punchthrough. A failure analysis revealed a large number of dislocations located in the corners of transistor cells. The majority of the detected dislocations were electrically inactive. Dislocation depth measurement indicated that only a small number of the dislocations penetrated deep into the channel, i.e., penetrated from source area to the boron-doped p-transistor channel. The transistor channel shortening caused by the enhanced phosphorus diffusion along the dislocations was determined as the root cause of the leakage. The diffusion spikes of the phosphorus atoms lengthened the n+ source layer, and the interface of the n+ and p-layer was shifted into the transistor channel at the site of the dislocation. Manufacturing process experiments related to the channel lengthening and the channel doping confirmed the theory of the dislocation-induced channel shortening. The occurrence of dislocations was attributed to the surface stress induced by the improper conditions of oxide growing and plasma etching in the affected regions.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

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OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2016

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY

ISSN

1530-4388

e-ISSN

1558-2574

Svazek periodika

16

Číslo periodika v rámci svazku

3

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

6

Strana od-do

396-401

Kód UT WoS článku

000384069500015

EID výsledku v databázi Scopus

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