Suppression of Dislocation-Induced Drain Leakage Current in Power VD MOSFET Structures

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21340%2F16%3A00311343" target="_blank" >RIV/68407700:21340/16:00311343 - isvavai.cz</a>

Výsledek na webu

<a href="http://ieeexplore.ieee.org/document/7544491/" target="_blank" >http://ieeexplore.ieee.org/document/7544491/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/TDMR.2016.2600539" target="_blank" >10.1109/TDMR.2016.2600539</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Suppression of Dislocation-Induced Drain Leakage Current in Power VD MOSFET Structures

Popis výsledku v původním jazyce

The investigated N-channel power vertical doublediffused metal-oxide-semiconductor field-effect-transistor (power VD MOSFET) suffered a drain-to-source current leakage (IDSS leakage). The leakage was caused by the dislocations located mainly in the N+ source area in the vicinity of the edge of the polycrystalline silicon gate. The stress induced by temperature gradients during wafer insertion into a furnace, its withdrawal from a furnace, and plasma damage were assumed to be the potential causes of the occurrence of dislocations. Inserting a wafer into a furnace and withdrawing it from a furnace at a slower pace during the steps of a high-temperature process' showed only a negligible suppression of the IDSS leakage. The plasma etching of the polycrystalline silicon gate byHBr (instead of the standard SF6) changed the pattern of IDSS failing transistors across a wafer (from the edge ring to continuous coverage), but the leakage was not suppressed. The IDSS leakage was completely eliminated by the 5-s shorter plasma-etching time (from 21 to 16 s) of the P+ implantation screen oxide. The plasma damage generated by the long etching time of the P+ implantation screen oxide was determined as the root cause of the occurrence of dislocations.

Název v anglickém jazyce

Suppression of Dislocation-Induced Drain Leakage Current in Power VD MOSFET Structures

Popis výsledku anglicky

The investigated N-channel power vertical doublediffused metal-oxide-semiconductor field-effect-transistor (power VD MOSFET) suffered a drain-to-source current leakage (IDSS leakage). The leakage was caused by the dislocations located mainly in the N+ source area in the vicinity of the edge of the polycrystalline silicon gate. The stress induced by temperature gradients during wafer insertion into a furnace, its withdrawal from a furnace, and plasma damage were assumed to be the potential causes of the occurrence of dislocations. Inserting a wafer into a furnace and withdrawing it from a furnace at a slower pace during the steps of a high-temperature process' showed only a negligible suppression of the IDSS leakage. The plasma etching of the polycrystalline silicon gate byHBr (instead of the standard SF6) changed the pattern of IDSS failing transistors across a wafer (from the edge ring to continuous coverage), but the leakage was not suppressed. The IDSS leakage was completely eliminated by the 5-s shorter plasma-etching time (from 21 to 16 s) of the P+ implantation screen oxide. The plasma damage generated by the long etching time of the P+ implantation screen oxide was determined as the root cause of the occurrence of dislocations.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

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OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

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Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2016

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY

ISSN

1530-4388

e-ISSN

1558-2574

Svazek periodika

16

Číslo periodika v rámci svazku

4

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

5

Strana od-do

556-560

Kód UT WoS článku

000389852400020

EID výsledku v databázi Scopus

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