SiC graphene FET with polydimethylglutharimide as a gate dielectric layer

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F14%3A00222420" target="_blank" >RIV/68407700:21230/14:00222420 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/ASDAM.2014.6998639" target="_blank" >http://dx.doi.org/10.1109/ASDAM.2014.6998639</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ASDAM.2014.6998639" target="_blank" >10.1109/ASDAM.2014.6998639</a>

Jazyk výsledku

angličtina

Název v původním jazyce

SiC graphene FET with polydimethylglutharimide as a gate dielectric layer

Popis výsledku v původním jazyce

Graphene is perspective material for future carbon based electronics, flexible electronics and other applications. The necessary condition for the commercial use is the high quality graphene growth and semiconductor technology compatible process of whole field effect transistor (FET). One of suitable method for large scale graphene monolayer preparation is the thermal annealing of semi-insulating SiC substrate. One important task of graphene FET process is reliable, cheap and simple gate structure preparation. In this work we present our results of using MicroChem Lift-Off Resist (LOR) layer as a dielectric layer for SiC graphene FETs. LOR resist is based on polydimethylglutharimide. Its unique properties enable to perform exceptionally well resolution imaging, easy process tuning, high yields and superior deposition line width control. In the case of polymer based dielectric layers the breakdown voltage is important parameter. We prepared two sets of different capacitor structures with LOR dielectric layer and Au/Cr electrodes. The first set exhibits very low breakdown voltages (about 3 V). The optimisation of the LOR layer deposition process in the second set increased the breakdown voltage over 40 V keeping the leakage current lower than 2 nA. The second process with LOR layer was used for the preparation of graphene FETs on SiC substrates. The first measurements show resistivity dependence on gate voltage.

Název v anglickém jazyce

SiC graphene FET with polydimethylglutharimide as a gate dielectric layer

Popis výsledku anglicky

Graphene is perspective material for future carbon based electronics, flexible electronics and other applications. The necessary condition for the commercial use is the high quality graphene growth and semiconductor technology compatible process of whole field effect transistor (FET). One of suitable method for large scale graphene monolayer preparation is the thermal annealing of semi-insulating SiC substrate. One important task of graphene FET process is reliable, cheap and simple gate structure preparation. In this work we present our results of using MicroChem Lift-Off Resist (LOR) layer as a dielectric layer for SiC graphene FETs. LOR resist is based on polydimethylglutharimide. Its unique properties enable to perform exceptionally well resolution imaging, easy process tuning, high yields and superior deposition line width control. In the case of polymer based dielectric layers the breakdown voltage is important parameter. We prepared two sets of different capacitor structures with LOR dielectric layer and Au/Cr electrodes. The first set exhibits very low breakdown voltages (about 3 V). The optimisation of the LOR layer deposition process in the second set increased the breakdown voltage over 40 V keeping the leakage current lower than 2 nA. The second process with LOR layer was used for the preparation of graphene FETs on SiC substrates. The first measurements show resistivity dependence on gate voltage.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

<a href="/cs/project/GAP108%2F11%2F0894" target="_blank" >GAP108/11/0894: Růst a zpracování gafenových vrstev na karbidu křemíku</a><br>

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2014

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

10th International Conference on Advanced Semiconductor Devices and Microsystems ASDAM 2014 Conference Proceedings

ISBN

978-1-4799-5475-9

ISSN

2475-2916

e-ISSN

—

Počet stran výsledku

4

Strana od-do

33-36

Název nakladatele

Slovak University of Technology in Bratislava

Místo vydání

Bratislava

Místo konání akce

Smolenice

Datum konání akce

20. 10. 2014

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000412228100008