Comprehensive behavioral model of dual-gate high voltage JFET and pinch resistor

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F16%3A00300815" target="_blank" >RIV/68407700:21230/16:00300815 - isvavai.cz</a>

Výsledek na webu

<a href="http://www.sciencedirect.com/science/article/pii/S0038110116300326" target="_blank" >http://www.sciencedirect.com/science/article/pii/S0038110116300326</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.sse.2016.05.001" target="_blank" >10.1016/j.sse.2016.05.001</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Comprehensive behavioral model of dual-gate high voltage JFET and pinch resistor

Popis výsledku v původním jazyce

Many analog technologies operate in large voltage range and therefore include at least one or more high voltage devices built from low doped layers. Such devices exhibit effects not covered by standard compact models, namely pinching (depletion) effects, in high voltage FETs often called quasisaturation. For example, the conventional compact JFET model is insufficient and oversimplified. Its scalability is controlled by the area factor, which only multiplies currents and capacitances but does not take into account existing 3-D effects. Also the optional second independent gate is missing. Therefore, the customized four terminal (4T) model written in Verilog-A (FitzPatrick and Miller, 2007; Sagdeo, 2007) was developed. It converges very well, its simulation speed is comparable with conventional compact models, and contains all required phenomena, including parasitic effects as, for example, impact ionization. This model has universal usage for many types of devices in various high voltage technologies such as stand-alone voltage dependent resistor, pinch resistor, drift area of power FET, part of special high side or start-up devices, and dual-gate JFET.

Název v anglickém jazyce

Comprehensive behavioral model of dual-gate high voltage JFET and pinch resistor

Popis výsledku anglicky

Many analog technologies operate in large voltage range and therefore include at least one or more high voltage devices built from low doped layers. Such devices exhibit effects not covered by standard compact models, namely pinching (depletion) effects, in high voltage FETs often called quasisaturation. For example, the conventional compact JFET model is insufficient and oversimplified. Its scalability is controlled by the area factor, which only multiplies currents and capacitances but does not take into account existing 3-D effects. Also the optional second independent gate is missing. Therefore, the customized four terminal (4T) model written in Verilog-A (FitzPatrick and Miller, 2007; Sagdeo, 2007) was developed. It converges very well, its simulation speed is comparable with conventional compact models, and contains all required phenomena, including parasitic effects as, for example, impact ionization. This model has universal usage for many types of devices in various high voltage technologies such as stand-alone voltage dependent resistor, pinch resistor, drift area of power FET, part of special high side or start-up devices, and dual-gate JFET.

Druh

J_x - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)

CEP obor

JA - Elektronika a optoelektronika, elektrotechnika

OECD FORD obor

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Projekt

<a href="/cs/project/TE01020186" target="_blank" >TE01020186: Centrum integrovaných družicových a pozemských navigačních technologií</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2016

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Solid-State Electronics

ISSN

0038-1101

e-ISSN

—

Svazek periodika

123

Číslo periodika v rámci svazku

9

Stát vydavatele periodika

NL - Nizozemsko

Počet stran výsledku

10

Strana od-do

133-142

Kód UT WoS článku

000379785900023

EID výsledku v databázi Scopus

2-s2.0-84969543350