Precise Subclock Period Delay in Digital Radar Target Simulation

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F25%3A00379915" target="_blank" >RIV/68407700:21230/25:00379915 - isvavai.cz</a>

Výsledek na webu

<a href="http://hdl.handle.net/10467/125825" target="_blank" >http://hdl.handle.net/10467/125825</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/TIM.2025.3546412" target="_blank" >10.1109/TIM.2025.3546412</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Precise Subclock Period Delay in Digital Radar Target Simulation

Popis výsledku v původním jazyce

In the digital radar target simulation, the period of the digital signal processing clock determines the tiniest step in signal delay. The signal delay determines the range of the simulated target. Therefore, the step in signal delay corresponds to the range resolution of the target simulator. This paper proposes three methods on how to increase signal delay resolution in the digital domain below the clock period. The improvement is from resolution in the range of tens of centimeters to several millimeters. The first technique optimizes the organization of the sample stream. The second is based on the deployment of the tapped delay line. And the third method utilizes precise phase shifting of the sampling clock. The proposed techniques can be combined to achieve the desired delay resolution. The methods are implemented and evaluated on an FPGA-based automotive radar target simulator in the 80 GHz band.

Název v anglickém jazyce

Precise Subclock Period Delay in Digital Radar Target Simulation

Popis výsledku anglicky

In the digital radar target simulation, the period of the digital signal processing clock determines the tiniest step in signal delay. The signal delay determines the range of the simulated target. Therefore, the step in signal delay corresponds to the range resolution of the target simulator. This paper proposes three methods on how to increase signal delay resolution in the digital domain below the clock period. The improvement is from resolution in the range of tens of centimeters to several millimeters. The first technique optimizes the organization of the sample stream. The second is based on the deployment of the tapped delay line. And the third method utilizes precise phase shifting of the sampling clock. The proposed techniques can be combined to achieve the desired delay resolution. The methods are implemented and evaluated on an FPGA-based automotive radar target simulator in the 80 GHz band.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

—

Návaznosti

I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Rok uplatnění

2025

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

IEEE Transactions on Instrumentation and Measurement

ISSN

0018-9456

e-ISSN

1557-9662

Svazek periodika

74

Číslo periodika v rámci svazku

February

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

11

Strana od-do

1-11

Kód UT WoS článku

001449658500037

EID výsledku v databázi Scopus

2-s2.0-105001260729