ZATPG: SAT-based Test Patterns Generator with Zero-Aliasing in Temporal Compaction
Identifikátory výsledku
Kód výsledku v IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F18%3A00321779" target="_blank" >RIV/68407700:21240/18:00321779 - isvavai.cz</a>
Výsledek na webu
<a href="https://www.sciencedirect.com/science/article/pii/S0141933118300966" target="_blank" >https://www.sciencedirect.com/science/article/pii/S0141933118300966</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1016/j.micpro.2018.05.001" target="_blank" >10.1016/j.micpro.2018.05.001</a>
Alternativní jazyky
Jazyk výsledku
angličtina
Název v původním jazyce
ZATPG: SAT-based Test Patterns Generator with Zero-Aliasing in Temporal Compaction
Popis výsledku v původním jazyce
Aliasing in test response compaction is an important source of fault coverage loss. Methods to avoid the aliasing mostly require modification of the compactor to some extent. This can lead to a higher compactor complexity and consequently to higher area overhead, longer signal propagation delays, etc. In contrast to this standard approach, we propose a novel method, the Zero-aliasing ATPG (ZATPG), which is able to reduce the aliasing for any compactor used, thus without need of the compactor modification or redesign. This is achieved by constraining the test pattern generation process (ATPG), so that patterns exhibiting no aliasing are produced directly. Aliasing in both the spatial and temporal compactors is assumed. The method is based on modification of very basic SAT-based ATPG principles, thus any SAT-based ATPG can be used for its purpose. Also, the method is general enough to be applicable to any compactor design. We demonstrate our method on MISR compactors based on LFSR and cellular automata, using the single stuck-at fault model. Our method is able to find a test with zero aliasing and complete fault coverage for smaller compactors than a conventional, unguided ATPG. Thus, the area overhead of the compactor can be reduced, while the complete fault coverage is preserved.
Název v anglickém jazyce
ZATPG: SAT-based Test Patterns Generator with Zero-Aliasing in Temporal Compaction
Popis výsledku anglicky
Aliasing in test response compaction is an important source of fault coverage loss. Methods to avoid the aliasing mostly require modification of the compactor to some extent. This can lead to a higher compactor complexity and consequently to higher area overhead, longer signal propagation delays, etc. In contrast to this standard approach, we propose a novel method, the Zero-aliasing ATPG (ZATPG), which is able to reduce the aliasing for any compactor used, thus without need of the compactor modification or redesign. This is achieved by constraining the test pattern generation process (ATPG), so that patterns exhibiting no aliasing are produced directly. Aliasing in both the spatial and temporal compactors is assumed. The method is based on modification of very basic SAT-based ATPG principles, thus any SAT-based ATPG can be used for its purpose. Also, the method is general enough to be applicable to any compactor design. We demonstrate our method on MISR compactors based on LFSR and cellular automata, using the single stuck-at fault model. Our method is able to find a test with zero aliasing and complete fault coverage for smaller compactors than a conventional, unguided ATPG. Thus, the area overhead of the compactor can be reduced, while the complete fault coverage is preserved.
Klasifikace
Druh
J<sub>imp</sub> - Článek v periodiku v databázi Web of Science
CEP obor
—
OECD FORD obor
20206 - Computer hardware and architecture
Návaznosti výsledku
Projekt
<a href="/cs/project/GA16-05179S" target="_blank" >GA16-05179S: Výzkum vztahů a společných vlastností spolehlivých a bezpečných architektur založených na programovatelných obvodech</a><br>
Návaznosti
S - Specificky vyzkum na vysokych skolach
Ostatní
Rok uplatnění
2018
Kód důvěrnosti údajů
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Údaje specifické pro druh výsledku
Název periodika
Microprocessors and Microsystems
ISSN
0141-9331
e-ISSN
1872-9436
Svazek periodika
2018
Číslo periodika v rámci svazku
61
Stát vydavatele periodika
NL - Nizozemsko
Počet stran výsledku
15
Strana od-do
43-57
Kód UT WoS článku
000441486700005
EID výsledku v databázi Scopus
2-s2.0-85048504988