Reducing Output Response Aliasing Using Boolean Optimization Techniques

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F23%3A00366279" target="_blank" >RIV/68407700:21240/23:00366279 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.1109/DDECS57882.2023.10139408" target="_blank" >https://doi.org/10.1109/DDECS57882.2023.10139408</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DDECS57882.2023.10139408" target="_blank" >10.1109/DDECS57882.2023.10139408</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Reducing Output Response Aliasing Using Boolean Optimization Techniques

Popis výsledku v původním jazyce

In digital circuit testing, output response compaction can have a significant impact on fault coverage. The loss of fault coverage is caused by aliasing in the output response compaction. Classical approaches to reducing (eliminating) fault aliasing are based on modifications of the compactor design or modifying precomputed test sequence. In this paper, we propose a completely different approach based on a dedicated test pattern generation algorithm. The algorithm generates a test sequence with minimal aliasing for targeted faults. As the generated test sequence is tailored to given static and dynamic compactor structures, any response compactor can be used without a change in the design. We expand on our previous work, zero-aliasing ATPG, and incorporate pseudo-Boolean optimization techniques in the process. The algorithm is evaluated using an LFSR-based MISR on a selection of benchmark circuits. A comparison with a state-of-the-art ATPG process without anti-aliasing measures is drawn.

Název v anglickém jazyce

Reducing Output Response Aliasing Using Boolean Optimization Techniques

Popis výsledku anglicky

In digital circuit testing, output response compaction can have a significant impact on fault coverage. The loss of fault coverage is caused by aliasing in the output response compaction. Classical approaches to reducing (eliminating) fault aliasing are based on modifications of the compactor design or modifying precomputed test sequence. In this paper, we propose a completely different approach based on a dedicated test pattern generation algorithm. The algorithm generates a test sequence with minimal aliasing for targeted faults. As the generated test sequence is tailored to given static and dynamic compactor structures, any response compactor can be used without a change in the design. We expand on our previous work, zero-aliasing ATPG, and incorporate pseudo-Boolean optimization techniques in the process. The algorithm is evaluated using an LFSR-based MISR on a selection of benchmark circuits. A comparison with a state-of-the-art ATPG process without anti-aliasing measures is drawn.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/EF16_019%2F0000765" target="_blank" >EF16_019/0000765: Výzkumné centrum informatiky</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2023

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems

ISBN

979-8-3503-3277-3

ISSN

2334-3133

e-ISSN

2473-2117

Počet stran výsledku

6

Strana od-do

33-38

Název nakladatele

IEEE - Electron Devices Society

Místo vydání

Piscataway

Místo konání akce

Tallinn

Datum konání akce

3. 5. 2023

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

001012062000006