Optically induced static power in combinational logic: Vulnerabilities and countermeasures

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F21%3A00350799" target="_blank" >RIV/68407700:21240/21:00350799 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.1016/j.microrel.2021.114281" target="_blank" >https://doi.org/10.1016/j.microrel.2021.114281</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.microrel.2021.114281" target="_blank" >10.1016/j.microrel.2021.114281</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Optically induced static power in combinational logic: Vulnerabilities and countermeasures

Popis výsledku v původním jazyce

Physical attacks, namely invasive, observation, and combined, represent a great challenge for today's digital design. Successful class of strategies adopted by industry, allowing hiding data dependency of the side channel emissions in CMOS is based on balancing. Although attacks on CMOS dynamic power represent a class of state-of-the-art attacks, vulnerabilities exploiting data dependency in CMOS static power and light-modulated static power were recently presented. In this paper, we describe structures and techniques developed to enhance and balance the power imprint of the traditional static CMOS bulk structures under invasive light attack. The novel standard cells designed according to the presented techniques in the TSMC180nm technology node were used to synthesize the dual-rail AES SBOX block. The behavior of the AES SBOX block composed of the novel cells is compared to classical approaches. Usage of novel cells enhances circuit security under invasive light attack while preserving comparable circuit resistance against state-of-the-art power attacks.

Název v anglickém jazyce

Optically induced static power in combinational logic: Vulnerabilities and countermeasures

Popis výsledku anglicky

Physical attacks, namely invasive, observation, and combined, represent a great challenge for today's digital design. Successful class of strategies adopted by industry, allowing hiding data dependency of the side channel emissions in CMOS is based on balancing. Although attacks on CMOS dynamic power represent a class of state-of-the-art attacks, vulnerabilities exploiting data dependency in CMOS static power and light-modulated static power were recently presented. In this paper, we describe structures and techniques developed to enhance and balance the power imprint of the traditional static CMOS bulk structures under invasive light attack. The novel standard cells designed according to the presented techniques in the TSMC180nm technology node were used to synthesize the dual-rail AES SBOX block. The behavior of the AES SBOX block composed of the novel cells is compared to classical approaches. Usage of novel cells enhances circuit security under invasive light attack while preserving comparable circuit resistance against state-of-the-art power attacks.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/EF16_019%2F0000765" target="_blank" >EF16_019/0000765: Výzkumné centrum informatiky</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2021

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Microelectronics Reliability

ISSN

0026-2714

e-ISSN

1872-941X

Svazek periodika

124

Číslo periodika v rámci svazku

September

Stát vydavatele periodika

NL - Nizozemsko

Počet stran výsledku

13

Strana od-do

—

Kód UT WoS článku

000687970500013

EID výsledku v databázi Scopus

2-s2.0-85111710941